00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030 #ifndef BASE_RDK230_M128_H
00031 #define BASE_RDK230_M128_H
00032
00033 #ifndef PB0
00034 # define PB0 (0)
00035 # define PB1 (1)
00036 # define PB2 (2)
00037 # define PB3 (3)
00038 # define PB4 (4)
00039 # define PB5 (5)
00040 # define PB6 (6)
00041 # define PB7 (7)
00042 # define PD4 (4)
00043 #endif
00044
00045 #ifndef DEFAULT_SPI_RATE
00046 # define DEFAULT_SPI_RATE (SPI_RATE_1_2)
00047 #endif
00048
00049
00050 #ifndef RADIO_TYPE
00051 # define RADIO_TYPE (RADIO_AT86RF230)
00052 #endif
00053
00054
00055
00056 #define DDR_TRX_RESET DDRB
00057 #define PORT_TRX_RESET PORTB
00058 #define MASK_TRX_RESET (_BV(5))
00060 #define TRX_RESET_INIT() DDR_TRX_RESET |= MASK_TRX_RESET
00061 #define TRX_RESET_HIGH() PORT_TRX_RESET |= MASK_TRX_RESET
00062 #define TRX_RESET_LOW() PORT_TRX_RESET &= ~MASK_TRX_RESET
00064 #define PORT_TRX_SLPTR PORTB
00065 #define DDR_TRX_SLPTR DDRB
00066 #define MASK_TRX_SLPTR (_BV(PB4))
00069 #define TRX_SLPTR_INIT() DDR_TRX_SLPTR |= MASK_TRX_SLPTR
00070
00071 #define TRX_SLPTR_HIGH() PORT_TRX_SLPTR |= MASK_TRX_SLPTR
00072
00073 #define TRX_SLPTR_LOW() PORT_TRX_SLPTR &= ~MASK_TRX_SLPTR
00074
00075
00076
00077 # define TRX_IRQ_vect TIMER1_CAPT_vect
00084 # define TRX_IRQ_INIT() do{\
00085 \
00086 TCCR1B |= (_BV(ICNC1) | _BV(ICES1));\
00087 TIFR = _BV(ICF1);\
00088 } while(0)
00089
00091 #define DI_TRX_IRQ() {TIMSK &= ~_BV(TICIE1);}
00092
00094 #define EI_TRX_IRQ() {TIMSK |= _BV(TICIE1);}
00095
00097 #define TRX_TSTAMP_REG ICR1
00098
00099
00100 #define DDR_SPI (DDRB)
00101 #define PORT_SPI (PORTB)
00103 #define SPI_MOSI _BV(PB2)
00104 #define SPI_MISO _BV(PB3)
00105 #define SPI_SCK _BV(PB1)
00106 #define SPI_SS _BV(PB0)
00108 #define SPI_DATA_REG SPDR
00114 static inline void SPI_INIT(uint8_t spirate)
00115 {
00116
00117 PORT_SPI |= SPI_SCK | SPI_SS;
00118 DDR_SPI |= SPI_MOSI | SPI_SCK | SPI_SS;
00119 DDR_SPI &= ~SPI_MISO;
00120
00121 SPCR = (_BV(SPE) | _BV(MSTR));
00122
00123 SPCR &= ~(_BV(SPR1) | _BV(SPR0) );
00124 SPSR &= ~_BV(SPI2X);
00125
00126 SPCR |= (spirate & 0x03);
00127 SPSR |= ((spirate >> 2) & 0x01);
00128
00129 }
00130
00132 #define SPI_SELN_LOW() uint8_t sreg = SREG; cli(); PORT_SPI &=~SPI_SS
00133
00134 #define SPI_SELN_HIGH() PORT_SPI |= SPI_SS; SREG = sreg
00135
00136 #define SPI_WAITFOR() do { while((SPSR & _BV(SPIF)) == 0);} while(0)
00137
00138
00139 #endif
00140