at86rf212.h

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00001 /* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf212.txt */
00002 
00003 /* Copyright (c) 2008 Axel Wachtler
00004    All rights reserved.
00005 
00006    Redistribution and use in source and binary forms, with or without
00007    modification, are permitted provided that the following conditions
00008    are met:
00009 
00010    * Redistributions of source code must retain the above copyright
00011      notice, this list of conditions and the following disclaimer.
00012    * Redistributions in binary form must reproduce the above copyright
00013      notice, this list of conditions and the following disclaimer in the
00014      documentation and/or other materials provided with the distribution.
00015    * Neither the name of the authors nor the names of its contributors
00016      may be used to endorse or promote products derived from this software
00017      without specific prior written permission.
00018 
00019    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00020    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00021    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00022    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00023    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00024    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00025    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00026    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00027    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00028    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00029    POSSIBILITY OF SUCH DAMAGE. */
00030 
00031 /* $Id: at86rf212_8h_source.html,v 1.1.1.4 2013/04/09 21:11:54 awachtler Exp $ */
00036 #ifndef AT86RF212_H
00037 #define AT86RF212_H (1)
00038 /* === Includes ============================================================== */
00039 
00040 /* === Externals ============================================================= */
00041 
00042 /* === Types ================================================================= */
00043 
00044 typedef uint8_t trx_ramaddr_t;
00045 typedef uint8_t trx_regval_t;
00046 typedef uint8_t trx_regaddr_t;
00047 
00048 /* === Macros ================================================================ */
00050 #define RG_TRX_STATUS (0x1)
00051 
00052   #define SR_CCA_DONE 0x1,0x80,7
00053 
00054   #define SR_CCA_STATUS 0x1,0x40,6
00055 
00056   #define SR_TRX_STATUS 0x1,0x1f,0
00057     #define P_ON (0)
00058     #define BUSY_RX (1)
00059     #define BUSY_TX (2)
00060     #define RX_ON (6)
00061     #define TRX_OFF (8)
00062     #define PLL_ON (9)
00063     #define TRX_SLEEP (15)
00064     #define BUSY_RX_AACK (17)
00065     #define BUSY_TX_ARET (18)
00066     #define RX_AACK_ON (22)
00067     #define TX_ARET_ON (25)
00068     #define RX_ON_NOCLK (28)
00069     #define RX_AACK_ON_NOCLK (29)
00070     #define BUSY_RX_AACK_NOCLK (30)
00071 
00072 #define RG_TRX_STATE (0x2)
00073 
00074   #define SR_TRAC_STATUS 0x2,0xe0,5
00075     #define TRAC_SUCCESS (0)
00076     #define TRAC_SUCCESS_DATA_PENDING (1)
00077     #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
00078     #define TRAC_CHANNEL_ACCESS_FAILURE (3)
00079     #define TRAC_NO_ACK (5)
00080     #define TRAC_INVALID (7)
00081 
00082   #define SR_TRX_CMD 0x2,0x1f,0
00083     #define CMD_NOP (0)
00084     #define CMD_TX_START (2)
00085     #define CMD_FORCE_TRX_OFF (3)
00086     #define CMD_RX_ON (6)
00087     #define CMD_TRX_OFF (8)
00088     #define CMD_PLL_ON (9)
00089     #define CMD_RX_AACK_ON (22)
00090     #define CMD_TX_ARET_ON (25)
00091 
00092 #define RG_TRX_CTRL_0 (0x3)
00093 
00094   #define SR_PAD_IO 0x3,0xc0,6
00095 
00096   #define SR_PAD_IO_CLKM 0x3,0x30,4
00097     #define CLKM_2mA (0)
00098     #define CLKM_4mA (1)
00099     #define CLKM_6mA (2)
00100     #define CLKM_8mA (3)
00101 
00102   #define SR_CLKM_SHA_SEL 0x3,0x8,3
00103 
00104   #define SR_CLKM_CTRL 0x3,0x7,0
00105     #define CLKM_no_clock (0)
00106     #define CLKM_1MHz (1)
00107     #define CLKM_2MHz (2)
00108     #define CLKM_4MHz (3)
00109     #define CLKM_8MHz (4)
00110     #define CLKM_16MHz (5)
00111 
00112 #define RG_TRX_CTRL_1 (0x4)
00113 
00114   #define SR_PA_EXT_EN 0x4,0x80,7
00115 
00116   #define SR_IRQ_2_EXT_EN 0x4,0x40,6
00117 
00118   #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
00119 
00120   #define SR_RX_BL_CTRL 0x4,0x10,4
00121 
00122   #define SR_SPI_CMD_MODE 0x4,0xc,2
00123 
00124   #define SR_IRQ_POLARITY 0x4,0x1,0
00125 
00126   #define SR_IRQ_MASK_MODE 0x4,0x2,1
00127 
00128 #define RG_PHY_TX_PWR (0x5)
00129 
00130   #define SR_PA_BOOST 0x5,0x80,7
00131 
00132   #define SR_GC_PA 0x5,0x60,5
00133 
00134   #define SR_TX_PWR 0x5,0x1f,0
00135 
00136 #define RG_PHY_RSSI (0x6)
00137 
00138   #define SR_RX_CRC_VALID 0x6,0x80,7
00139 
00140   #define SR_RND_VALUE 0x6,0x60,5
00141 
00142   #define SR_RSSI 0x6,0x1f,0
00143 
00144 #define RG_PHY_ED_LEVEL (0x7)
00145 
00146   #define SR_ED_LEVEL 0x7,0xff,0
00147 
00148 #define RG_PHY_CC_CCA (0x8)
00149 
00150   #define SR_CCA_REQUEST 0x8,0x80,7
00151 
00152   #define SR_CCA_MODE 0x8,0x60,5
00153 
00154   #define SR_CHANNEL 0x8,0x1f,0
00155 
00156 #define RG_CCA_THRES (0x9)
00157 
00158   #define SR_CCA_ED_THRES 0x9,0xf,0
00159 
00160 #define RG_SFD_VALUE (0xb)
00161 
00162   #define SR_SFD_VALUE 0xb,0xff,0
00163 
00164 #define RG_TRX_CTRL_2 (0xc)
00165 
00166   #define SR_RX_SAFE_MODE 0xc,0x80,7
00167 
00168   #define SR_TRX_OFF_AVDD_EN 0xc,0x40,6
00169 
00170   #define SR_BPSK_OQPSK 0xc,0x8,3
00171 
00172   #define SR_SUB_MODE 0xc,0x4,2
00173 
00174   #define SR_OQPSK_DATA_RATE 0xc,0x3,0
00175 
00176 #define RG_ANT_DIV (0xd)
00177 
00178   #define SR_ANT_SEL 0xd,0x80,7
00179 
00180   #define SR_ANT_EXT_SW_EN 0xd,0x4,2
00181 
00182   #define SR_ANT_CTRL 0xd,0x3,0
00183 
00184 #define RG_IRQ_MASK (0xe)
00185 
00186   #define SR_MASK_BAT_LOW 0xe,0x80,7
00187 
00188   #define SR_MASK_TRX_UR 0xe,0x40,6
00189 
00190   #define SR_MASK_AMI 0xe,0x20,5
00191 
00192   #define SR_MASK_CCA_ED_READY 0xe,0x10,4
00193 
00194   #define SR_MASK_TRX_END 0xe,0x8,3
00195 
00196   #define SR_MASK_RX_START 0xe,0x4,2
00197 
00198   #define SR_MASK_PLL_LOCK 0xe,0x1,0
00199 
00200   #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
00201 
00202 #define RG_IRQ_STATUS (0xf)
00203 
00204   #define SR_BAT_LOW 0xf,0x80,7
00205 
00206   #define SR_TRX_UR 0xf,0x40,6
00207 
00208   #define SR_AMI 0xf,0x20,5
00209 
00210   #define SR_CCA_ED_READY 0xf,0x10,4
00211 
00212   #define SR_TRX_END 0xf,0x8,3
00213 
00214   #define SR_RX_START 0xf,0x4,2
00215 
00216   #define SR_PLL_LOCK 0xf,0x1,0
00217 
00218   #define SR_PLL_UNLOCK 0xf,0x2,1
00219 
00220 #define RG_VREG_CTRL (0x10)
00221 
00222   #define SR_AVREG_EXT 0x10,0x80,7
00223 
00224   #define SR_AVDD_OK 0x10,0x40,6
00225 
00226   #define SR_DVREG_EXT 0x10,0x8,3
00227 
00228   #define SR_DVDD_OK 0x10,0x4,2
00229 
00230 #define RG_BATMON (0x11)
00231 
00232   #define SR_BATMON_OK 0x11,0x20,5
00233 
00234   #define SR_BATMON_HR 0x11,0x10,4
00235 
00236   #define SR_BATMON_VTH 0x11,0xf,0
00237 
00238 #define RG_XOSC_CTRL (0x12)
00239 
00240   #define SR_XTAL_MODE 0x12,0xf0,4
00241 
00242   #define SR_XTAL_TRIM 0x12,0xf,0
00243 
00244 #define RG_CC_CTRL_0 (0x13)
00245 
00246   #define SR_CC_NUMBER 0x13,0xff,0
00247 
00248 #define RG_CC_CTRL_1 (0x14)
00249 
00250   #define SR_CC_BAND 0x14,0x4,2
00251 
00252   #define SR_BAND 0x14,0x1,0
00253 
00254   #define SR_CC_ 0x14,0x2,1
00255 
00256 #define RG_RX_SYN (0x15)
00257 
00258   #define SR_RX_PDT_DIS 0x15,0x80,7
00259 
00260   #define SR_RX_PDT_LEVEL 0x15,0xf,0
00261 
00262 #define RG_RF_CTRL_0 (0x16)
00263 
00264   #define SR_PA_LT 0x16,0xc0,6
00265 
00266   #define SR_GC_TX_OFFS 0x16,0x3,0
00267 
00268 #define RG_XAH_CTRL_1 (0x17)
00269 
00270   #define SR_CSMA_LBT_MODE 0x17,0x80,7
00271 
00272   #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
00273 
00274   #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
00275 
00276   #define SR_AACK_ACK_TIME 0x17,0x4,2
00277 
00278   #define SR_AACK_PROM_MODE 0x17,0x2,1
00279 
00280 #define RG_FTN_CTRL (0x18)
00281 
00282   #define SR_FTN_START 0x18,0x80,7
00283 
00284 #define RG_RF_CTRL_1 (0x19)
00285 
00286   #define SR_RF_MC 0x19,0xf0,4
00287 
00288 #define RG_PLL_CF (0x1a)
00289 
00290   #define SR_PLL_CF_START 0x1a,0x80,7
00291 
00292 #define RG_PLL_DCU (0x1b)
00293 
00294   #define SR_PLL_DCU_START 0x1b,0x80,7
00295 
00296 #define RG_PART_NUM (0x1c)
00297 
00298   #define SR_PART_NUM 0x1c,0xff,0
00299     #define RF212A_PART_NUM (7)
00300 
00301 #define RG_VERSION_NUM (0x1d)
00302 
00303   #define SR_VERSION_NUM 0x1d,0xff,0
00304     #define RF212A_VERSION_NUM (1)
00305 
00306 #define RG_MAN_ID_0 (0x1e)
00307 
00308   #define SR_MAN_ID_0 0x1e,0xff,0
00309 
00310 #define RG_MAN_ID_1 (0x1f)
00311 
00312   #define SR_MAN_ID_1 0x1f,0xff,0
00313 
00314 #define RG_SHORT_ADDR_0 (0x20)
00315 
00316   #define SR_SHORT_ADDR_0 0x20,0xff,0
00317 
00318 #define RG_SHORT_ADDR_1 (0x21)
00319 
00320   #define SR_SHORT_ADDR_1 0x21,0xff,0
00321 
00322 #define RG_PAN_ID_0 (0x22)
00323 
00324   #define SR_PAN_ID_0 0x22,0xff,0
00325 
00326 #define RG_PAN_ID_1 (0x23)
00327 
00328   #define SR_PAN_ID_1 0x23,0xff,0
00329 
00330 #define RG_IEEE_ADDR_0 (0x24)
00331 
00332   #define SR_IEEE_ADDR_0 0x24,0xff,0
00333 
00334 #define RG_IEEE_ADDR_1 (0x25)
00335 
00336   #define SR_IEEE_ADDR_1 0x25,0xff,0
00337 
00338 #define RG_IEEE_ADDR_2 (0x26)
00339 
00340   #define SR_IEEE_ADDR_2 0x26,0xff,0
00341 
00342 #define RG_IEEE_ADDR_3 (0x27)
00343 
00344   #define SR_IEEE_ADDR_3 0x27,0xff,0
00345 
00346 #define RG_IEEE_ADDR_4 (0x28)
00347 
00348   #define SR_IEEE_ADDR_4 0x28,0xff,0
00349 
00350 #define RG_IEEE_ADDR_5 (0x29)
00351 
00352   #define SR_IEEE_ADDR_5 0x29,0xff,0
00353 
00354 #define RG_IEEE_ADDR_6 (0x2a)
00355 
00356   #define SR_IEEE_ADDR_6 0x2a,0xff,0
00357 
00358 #define RG_IEEE_ADDR_7 (0x2b)
00359 
00360   #define SR_IEEE_ADDR_7 0x2b,0xff,0
00361 
00362 #define RG_XAH_CTRL_0 (0x2c)
00363 
00364   #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
00365 
00366   #define SR_SLOTTED_OPERATION 0x2c,0x1,0
00367 
00368   #define SR_MAX_CSMA_RETRIES 0x2c,0xe,1
00369 
00370 #define RG_CSMA_SEED_0 (0x2d)
00371 
00372   #define SR_CSMA_SEED_0 0x2d,0xff,0
00373 
00374 #define RG_CSMA_SEED_1 (0x2e)
00375 
00376   #define SR_AACK_FVN_MODE 0x2e,0xc0,6
00377 
00378   #define SR_AACK_SET_PD 0x2e,0x20,5
00379 
00380   #define SR_AACK_DIS_ACK 0x2e,0x10,4
00381 
00382   #define SR_AACK_I_AM_COORD 0x2e,0x8,3
00383 
00384   #define SR_CSMA_SEED_1 0x2e,0x7,0
00385 
00386 #define RG_CSMA_BE (0x2f)
00387 
00388   #define SR_MAX_BE 0x2f,0xf0,4
00389 
00390   #define SR_MIN_BE 0x2f,0xf,0
00391 
00392 #define RADIO_NAME "AT86RF212"
00393 
00394 #define RADIO_PART_NUM (RF212A_PART_NUM)
00395 
00396 #define RADIO_VERSION_NUM (RF212A_VERSION_NUM)
00397 
00399 #define TRX_CMD_RW           (_BV(7) | _BV(6))
00400 
00401 #define TRX_CMD_RR           (_BV(7))
00402 
00403 #define TRX_CMD_FW           (_BV(6) | _BV(5))
00404 
00405 #define TRX_CMD_FR           (_BV(5))
00406 
00407 #define TRX_CMD_SW           (_BV(6))
00408 
00409 #define TRX_CMD_SR           (0)
00410 
00411 #define TRX_CMD_RADDR_MASK   (0x3f)
00412 
00414 #define TRX_RESET_TIME_US    (6)
00415 
00417 #define TRX_INIT_TIME_US     (510)
00418 
00420 #define TRX_PLL_LOCK_TIME_US     (180)
00421 
00422 
00424 #define TRX_CCA_TIME_US     (140)
00425 
00427 #define TRX_IRQ_PLL_LOCK   _BV(0)
00428 
00430 #define TRX_IRQ_PLL_UNLOCK _BV(1)
00431 
00433 #define TRX_IRQ_RX_START   _BV(2)
00434 
00436 #define TRX_IRQ_TRX_END    _BV(3)
00437 
00439 #define TRX_IRQ_CCA_ED     _BV(4)
00440 
00442 #define TRX_IRQ_AMI        _BV(5)
00443 
00445 #define TRX_IRQ_UR         _BV(6)
00446 
00448 #define TRX_IRQ_BAT_LOW    _BV(7)
00449 
00451 #define TRAC_SUCCESS (0)
00452 
00453 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
00454 
00455 #define TRAC_NO_ACK (5)
00456 
00457 
00459 #define TRX_MIN_CHANNEL (0)
00460 
00462 #define TRX_MAX_CHANNEL (10)
00463 
00465 #define TRX_NB_CHANNELS (11)
00466 
00472 #define TRX_SUPPORTED_CHANNELS  (0x00007ffUL)
00473 
00478 #define TRX_SUPPORTED_PAGES     (42)
00479 #define TRX_SUPPORTS_BAND_700 (1)
00480 #define TRX_SUPPORTS_BAND_800 (1)
00481 #define TRX_SUPPORTS_BAND_900 (1)
00482 
00484 #define TRX_BPSK20    (0)
00485 
00487 #define TRX_BPSK40    (4)
00488 
00490 #define TRX_OQPSK100  (8)
00491 
00493 #define TRX_OQPSK200  (9)
00494 
00496 #define TRX_OQPSK400  (10)
00497 #define TRX_OQPSK400_1  (11)
00498 
00500 #define TRX_OQPSK250  (12)
00501 
00503 #define TRX_OQPSK500  (13)
00504 
00506 #define TRX_OQPSK1000 (14)
00507 #define TRX_OQPSK1000_1 (15)
00508 
00509 #define TRX_NONE      (255)
00510 
00511 #endif /* ifndef AT86RF212_H */

This documentation for µracoli was generated on Tue Apr 9 2013 by  doxygen 1.7.1